1. Field of the Invention
Embodiments in accordance with the present invention generally pertain to electronic design automation. In particular, embodiments in accordance with the present invention pertain to simulation models used for system-level modeling.
2. Related Art
A system on a chip (SOC) may be relatively large and complex, incorporating multiple processors as well as other devices that support display, memory and keypad capabilities. System-level models are used to simulate systems such as SOCs during the design process (e.g., before they are implemented in hardware). Using system-level simulation, software that will run on systems such as SOCs can be designed and tested in parallel with the hardware design.
The computational complexity of system-level simulation models means that the simulation runs slower relative to the speed of execution of an actual hardware platform. Increasing the speed of simulation is one of the goals of model designers.
In simulation, clocks are normally modeled as modules that update a signal based on the clock's properties (e.g., period and duty cycle). This can mean that a clock model will generate an event for the falling edge and rising edge of the clock being modeled. For example, in SystemC coding:
void clock_gen( ) {While (true) {clk = true;wait(negedge_time);clk = false;wait(posedge_time);}}
According to the above, the simulation kernel will have activity for every event. Even if the clock is the only module in the system, the maximum simulation speed (in cycles per second) is limited by how fast the kernel can schedule and run the clock process.
Higher performance modeling can be achieved by not using a clock object and letting the simulation advance in steps larger than one clock tick. That is, instead of running the simulation at every clock cycle or edge, larger time steps can be used. For example:
void process( ) {//process sensitive to some start of transactionevent...// wait for one clockwait(10,SC_NS); //no clock port, wait based on time (10 nanoseconds)...}
While larger time steps can accelerate execution of the simulation, this is balanced by a loss of accuracy. Developers of new products (software or hardware) are interested in seeing simulation results that are as realistic as can be reasonably expected, and so a loss of accuracy may not be tolerable. To achieve the desired accuracy, some devices in a system such as an SOC may be simulated using smaller time steps. Consequently, the simulation will proceed more slowly, because the speed of the system simulation will be limited by the slowest of the device simulations.